RTL Design Engineer - Fpga/asic/verilog/vhdl

Job Description

• ,You will contribute to the specification, micro architecture and RTL design of high-performance, energy-efficient interconnects. , , This opportunity is specific to a confidential project, and as part of this small and talented team, you will be able to expand your technical breadth relating to leading-edge coherent interconnects, including multi-chip. , , - Coherent Interconnect Micro-architecture specification and RTL design. , , - Prior RTL design experience is required. , , - Track Record and expertise in implementing complex FPGA IP design and resolving complex resource and timing closure challenges. , , - Education BS or MS in Electrical Engineering or Computer Engineering , , Experience : 8 to 12 years of experience in reputed product based Semi conductor companies , , - ASIC/FPGA design experience , , - Verilog, VHDL , , - Graphics, Image Processing , , - Synthesis, Simulation, Microarchitecture , , Please refer to the Job description above

Job Summary